1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a gate/data pad structure of a liquid crystal display device and a fabrication method thereof.
2. Description of the Related Art
A current progression in information technology has greatly necessitated a flat panel display device that is thinner, lighter and less power-consuming. Among various types of flat panel display devices, a liquid crystal display (LCD) device with excellent color reproducibility has been a recent focus of development.
Generally, the LCD device displays an image by adjusting a degree of light transmission. That is, in the LCD device, two substrates with electrodes thereon are arranged facing each and a liquid crystal material is injected into the two substrates. After injecting the liquid crystal material, a predetermined voltage is supplied to the two electrodes, mobilizing liquid crystals using an electric field created through the supplied voltage for displaying the image.
Hereinafter, a typical structure of a LCD device will be described with reference to the accompanying drawings.
FIG. 1 is an enlarged top view illustrating a portion of an array substrate which is a bottom substrate of a LCD device. In particular, FIG. 1 illustrates an array substrate of a twisted nematic (TN) mode LCD device.
As mentioned above, the bottom substrate 10 is often called an array substrate, and a plurality of thin film transistors T which are switching devices are arranged in a matrix type. There is a plurality of gate lines 25 crossing a plurality of data lines 27 at corresponding thin film transistors T. A pixel region P is defined by the region formed by the crossing of the gate lines 25 and the data lines 27.
A gate pad 29 and a data pad 31 each for receiving a signal from an external source are formed at one edge side of each gate line 25 and each data line 27, respectively. Each of the thin film transistors T includes a gate electrode 21, a source electrode 60, a drain electrode 62, and an active layer 41 disposed above the gate electrode 21. A pixel electrode 91 is formed at the pixel region P.
FIG. 2 illustrates cross-sectional views of the pixel region, a gate pad region and a data pad region taken along lines II-II, III-III and IV-IV depicted in FIG. 1, respectively. The same reference numerals are used for the same configuration elements described in FIG. 1.
As illustrated, the gate electrode 21 made of a conductive material such as a metal is formed on the bottom substrate 10 and is overlaid with a gate insulation layer 30 formed with a material such as silicon nitride or silicon oxide.
The active layer 41 made of amorphous silicon is formed on the gate insulation layer 30, and a pair of ohmic contact layers 51 and 52 is formed on the active layer 41. Herein, the ohmic contact layers 51 and 52 are impurity doped amorphous silicon layers. On top of the pair of ohmic contact layers 51 and 52, the source electrode 60 and the drain electrode 62 made of a conductive material such as a metal are formed. Herein, the source electrode 60, the drain electrode 62, and the gate electrode 21 constitute the thin film transistor T illustrated in FIG. 1.
Next, a passivation layer 70 made of silicon nitride, silicon oxide or an organic insulation material is formed over the source electrode 60 and the drain electrode 62. The passivation layer 70 includes a contact hole 71 exposing the drain electrode 62. The pixel electrode 91 made of a transparent conductive material is formed on the passivation layer 70 and is connected with the drain electrode 62 through the contact hole 71.
Furthermore, the gate line 25 is formed on the bottom substrate 10, and the gate pad 29 is formed with a predetermined area at one edge side of the gate line 25. The gate pad 29 includes: the bottom substrate 10; a gate pad bottom electrode 28; the gate insulation layer 30; the passivation layer 70; a gate pad contact hole 59; and a gate pad terminal electrode 65. More specifically, in the gate pad 29, the gate pad bottom electrode 28 is formed on the bottom substrate 10, and the gate insulation layer 30 is formed over the bottom substrate 10 provided with the gate insulation layer 30. Then, the gate insulation layer 30 and the passivation layer 70 are etched to form the gate pad contact hole 59 exposing the gate pad bottom electrode 28. The gate pad terminal electrode 65 is formed over the gate pad contact hole 59 through which the gate pad terminal electrode 65 is connected with the gate pad bottom electrode 28.
Meanwhile, the data line 27 is formed on the gate insulation layer 30 and extends in a perpendicular direction to the source electrode 60. At one edge side of the data line 27, the data pad 31 is formed with a predetermined area.
Also, as for the data pad 31, the passivation layer 70 formed over the bottom substrate 10 provided with a data pad bottom electrode 32 is etched to form a data pad contact hole 61 exposing the data pad bottom electrode 32. A data pad terminal electrode 67 is formed over the data pad contact hole 61, thereby being connected with the data pad bottom electrode 32.
At this time, predetermined portions of the gate insulation layer 30 and the passivation layer 70 are etched to form the gate pad contact hole 59, whereas a predetermined portion of the passivation layer 70 is etched to form the data pad contact hole 61. In the course of etching these predetermined portions, the gate pad contact hole 59 and the data pad contact hole 61 are sloped steeply.
As described above, the gate pad terminal electrode 65 and the data pad terminal electrode 67 both formed by using indium tin oxide (ITO) or indium zinc oxide (IZO) are patterned respectively on the gate pad bottom electrode 28 and the data pad bottom electrode 32 each formed with a predetermined area at one edge side of the gate line 25 and of the data line 27.
If the gate line 25 and the data line 27 are made of aluminum or an aluminum alloy (AlNd), an oxide layer is formed when the gate pad bottom electrode 28 and the data pad bottom electrode 32 are in contact with the gate pad terminal electrode 65 and the data pad terminal electrode 67, respectively.
The oxide layer hinders the gate pad terminal electrode 65 and the data pad terminal electrode 67 from directly contacting the aluminum-based material used for the gate line 25 and the data line 27 resulting in poor electrical contact. Hence, a buffer layer made of molybdenum (Mo) is formed between the aluminum-based material and each of the gate pad terminal electrode 65 and the data pad terminal electrode 67.
That is, by forming the gate line 25 and the data line 27 as a dual layer of the aluminum-based layer (AlNd) and the molybdenum layer (Mo), it is possible to eliminate the oxide layer generated when the gate line bottom electrode 28 and the data line bottom electrode 32 contact the gate pad terminal electrode 65 and the data pad terminal electrode 67, respectively.
FIG. 3 is a cross-sectional view illustrating a structure of a related art gate pad in detail. The gate pad structure is illustrated as an example; this structure can also be applied to the data pad.
As illustrated, a gate pad bottom electrode 310 is formed on a substrate 300 in a dual structure including an aluminum alloy layer 312 and a molybdenum layer 314. One exemplary material for the aluminum alloy layer 312 is AlNd.
Particularly, the molybdenum layer 314 is formed in a thickness of about 500 Å, while the aluminum alloy layer 312 is formed in a thickness of about 2,000 Å. Also, a thickness of a gate insulation layer 320 formed over the gate pad bottom electrode 310 and that of a passivation layer 330 formed on the gate insulation layer 320 are about 4,000 Å and about 2,000 Å, respectively.
After the formation of the passivation layer 330, a contact hole 340 is formed by performing an etching process for the purpose of making a contact between the gate pad bottom electrode 310 and a gate pad terminal electrode 350.
However, in the course of performing the above related art etching process, over-etching frequently occurs, resulting in a complete removal of the passivation layer 330, the gate insulation layer 320 and the molybdenum layer 314.
That is, if the molybdenum layer 314 is etched through the over-etching, the gate pad terminal electrode 350 made of ITO or IZO makes a direct contact with the aluminum alloy layer 312. As a result, corrosion may occur at an interface between the aluminum alloy layer 312 and the gate pad terminal electrode 350.
In addition, during the related art etching process, predetermined portions of the passivation layer 330 and the gate insulation layer 320 are etched concurrently, causing the contact hole 340 to be sloped steeply. This steeply sloped region of the contact hole 340 is denoted with a reference numeral 360.
Accordingly, when the gate pad terminal electrode 350 is formed over the contact hole 340, a step-coverage characteristic of the gate pad terminal electrode 350 around the steeply sloped region 360 becomes poor, further resulting in a disconnection of the gate pad terminal electrode 350.
Moreover, the aluminum alloy layer 312 of the gate pad bottom electrode 310 may become exposed around the disconnected portion of the gate pad terminal electrode 350, causing a corrosion problem.